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Review of the development of PCB technology

According to the development of existing literature and PCB technology, the author divides the development process of PCB technology into the following three stages (different from the traditional division stage):

The first stage, from the beginning of the 20th century to 1950, the embryonic period, that is, the early stage of PCB industrialization, at this time the PCB industry has not yet formed;

The second stage, from 1950 to 1990, the growth period, that is, the early stage of the PCB industrialization period, at which time PCB formed the industry;

The third stage, from 1990 to the present, the development period, which is the middle period of the PCB industrialization period

Embryonic period

The iconic PCB technologies at this stage are:

(1) In 1925, Charles Ducas of the United States proposed forming a trench on a dielectric filled with a conductive paste and then electroplating to form a conductor.

(2) In 1936, Paul Ai Sile (Paul Eisler, an Austrian who was unemployed in the UK, graduated from the Vienna University of Technology in 1930, not a doctoral degree in the industry) experimented with the use of foil technology in the radio (A foil membrane technology) In 1943, he applied for a patent covering the ink etching method during the Technograph project invested by the British company Henderson & Spalding (this patent was officially published on June 21, 1950, but was divided into three separate patents: GB639111 (core), GB639178, and GB639179).

(3) In 1936, Japan's Miyamoto Kinosuke (Miyata Hiroyuki, Miyata Manufacturing Co., Ltd.) applied for a patent for the wiring method (Patent No.: 119384, metallization wiring method, see: http ://sts.kahaku.go.jp/sts/detail.php?no=104510511002&).

(4) In 1938, glass fiber began to be produced.

(5) In 1941, the United States introduced a class of PCB technology in the military (painting copper paste on talc as a wire for mortars).

(6) In 1947, an epoxy resin was introduced as a substrate.

(7) In 1947, Singal Corps of the United States solved the problem of bonding large-area copper foil to insulating materials.

(8) In 1947, the United States NBS (National Bureau of Standards) researched the formation of coils, capacitors, resistors (printed components) and other technologies.

(9) In 1950, Japan applied silver as a conductor on a glass substrate; copper foil was used as a conductor on a phenolic resin paper-based material.

(10) After 1950, the manufacturing technology of Printed Circuit began to be accepted and widely used. At this time, etched foil was the mainstream technology.

Looking at it now, the methods of Charles Ducas and Miyamoto Kinosuke among the three people represented at the time belonged to the semi-additive method, and the method of Paul Ai Sile belonged to the subtractive method. Since the subtraction method was first industrialized in the PCB industry and the most widely used, Paul Ai Sile is considered to be the father of PCB. Objectively speaking, the PCB industry has taken a huge contribution from the embryonic form, birth, development, and innovation, and the US, European, and Japanese practitioners (especially some electronic giants) have contributed greatly.

Growth period

The iconic PCB technologies at this stage are:

(1) In 1953, DuPont of the United States applied for a patent for polyimide products (Patent No.: US2710853A), which required protection of polypyrylene imide resin and its films and tubes (Phompson's polyacyl in the 1960s) Imine film (Kapton®), Vespel® and Pyre ML® are commercially available);

(2) In 1953, Motorola developed a double-panel plated through-hole; before and after 1955, Toshiba Corporation of Japan proposed a process for forming copper oxide on the surface of copper foil, and a copper-clad laminate was introduced. These two methods have also been applied to multilayer boards in the future, and they have also contributed to the advent of multi-layer boards. Multilayer boards have led to a significant increase in wiring rates; since then, PCBs have been widely used.

(3) In 1954, the United States General Electric proposed the use of lead-tin alloy as a corrosion-resistant metal conductor protective layer manufacturing technology.

(4) In 1960, V. Dahlgreen invented the process of bonding metal foil to a thermoplastic film to form a circuit pattern, which is the beginning of FPC products.

(5) In 1960, Japan began to make multilayer boards from epoxy resin glass cloth substrates.

      (6) In 1963, Hazeltine Research Inc. of the United States applied for a patent for electroplated through-hole fabrication of multi-layer boards.

(7) In 1964, Western Electric Company of the United States developed a metal core board with high heat dissipation.

(8) In 1965, Japan developed FR4 and FR5 copper clad laminates of epoxy resin glass cloth substrates.

(9) In 1967, RJ's Robert J. Ryan and others applied for a patent for the manufacture of laminated multi-layer boards (US3756891, whose core is Plated-up technology), and the industry first proposed layering technology.

(10) In 1968, DuPont of the United States invented the photopolymer dry film (Riston®).

(11) In 1969, Sanyo Corporation of Japan developed a metal-insulated copper clad laminate.

(12) In 1969, Philips, the Netherlands, developed FPC (FD-R) made of polyimide.

(13) In 1977, Japan's Mitsubishi Gas Chemical Company developed BT resin.

(14) In 1979, Pactel invented the "Pactel law" layering method (the inter-layer connection uses a metal column structure).

(15) In 1982, Glen E. Leinbach et al. of HP Corporation of the United States developed a Multilayer substrate with a micro-blind hole (called "Finstrate", which uses a laser to process a blind hole with a hole diameter of 0.125 mm).

(16) In 1984, NTT invented a ceramic substrate with a "Copper Polyimide Act" with a thin film circuit. The insulating layer is a photosensitive resin, and the via holes are formed by exposure and development of the photosensitive resin.

(17) In 1988, Siemens developed a 10-layer and above "Microwiring Substrate" laminated PCB for large computers, using a excimer laser to process blind holes.

Development period

Iconic technology

The iconic PCB technologies at this stage are:

(1) In 1990, Japan's IBM (Yasu) developed a SLC (Surface Laminar Circuit) carrier for Flip Chip connection of semiconductors, see Figure 13 and Figure 14 process flow.

(2) In 1993, Motorola's Paul T. Lin and others applied for a BGA package patent (US5216278 A), which opened the era of organic carrier packaging.

(3) In 1995, Matsushita Electronics Co., Ltd. developed a laminated PCB process of ALIVH (Any Layer Interstitial Via Hole structure).

(4) In 1996, Toshiba developed the process of B2it (Buried Bump Interconnection Technology).

(5) Japan's North developed the NMBI (Neo-Manhattan Bump Interconnection, new type of column bump interconnect technology) process, and later the US Tessera improved the process

(6) Ibiden developed the FVSS (Free Via Stackedup Structure) process, originally called SSP technology (Single Step Process), now called FVSS.

Looking at these layering techniques, the core is how to achieve interlayer interconnection. There are two ways to achieve interlayer interconnection. One is to achieve conduction through direct hole formation, electroplating or filling of conductive materials (such as SLC, HITAVIA, ALIVH, FVSS, VIL); the second is to use bumps (indirectly into holes) to directly achieve mutual Connected (such as B2it, NMBI). It is worth mentioning that most of the proponents of these new technologies are Japanese companies. It can be said that Japanese companies have contributed a lot to the industry in the development of laminated PCB technology (especially new process tests, new material development, new equipment development). ).

For the direct hole forming process, there were five main types of hole forming techniques: photoinduced, laser (UV and CO2), plasma, excimer, and mechanical drill. Due to the limitations of other hole forming technologies or due to the growing and mature laser technology, the most widely used in the industry is the laser hole forming process. For the indirect hole forming technology, due to the limitations of its technology or the development and maturity of the laser hole forming + plating hole filling process, the application is gradually decreasing. Therefore, the current lamination process is mainly laser drilling + electroplating and hole filling process.

At the time, based on this layered technology, according to the actual needs of the end customers, the industry formed two directions: HDI (Subtractive reduction method based, based on FR-4 material, assembly technology) and Substrate (MSAP/SAP half). The additive process is based on BT, ABF materials, and packaging technology. The process flow of the line formation method is shown in Figure 19. However, since 2014, HDI and Substrate have begun to merge with products such as Apple's mobile phones and watches.


For HDI products, in the past 20 years, based on laser hole forming + electroplating copper process, HDI process has undergone the following changes: ConformalMask→LargeWindow→SmallWindow→LDD (LaserDirect Drilling, CO2 laser direct drilling, see Figure 20 to Figure 22. Note: Substrate uses UV laser drilling and CO2 laser drilling); copper plating → copper filling; film contact exposure → LDI (Laser Direct Imaging); first order → second order → multi-order → AnyLayer (soft and hard combination The board's hard board area is also used by AnyLayer technology).

At present, HDI's representative product (Any Layer structure) is applied to the mobile phone motherboard. Take Samsung's Note 8 motherboard as an example. It is designed as a 12-layer Any Layer with a BGA pitch of 350mm and a board thickness of 650mm.

Recently, regarding HDI, the new technology developed by the industry has ultra-thin plates, Cavity (cavity plate, or step plate, divided into Non Component Type non-pad type and Component Type pad type), just - The rigid plate area of the flexible bonding plate is an Any Layer or the like.


At present, Substrate's representative products are in mobile phones, computer main processors and other applications.

Recently, regarding Substrate, the industry has developed many new processes. Due to the special nature of Substrate products, many processes are developed in conjunction with the back-end packaging, even directly by the packaging company or chip design company.

Some representative technologies are:

(1) BBUL: Intel's Steven N. Towle et al. proposed BBUL (Bumpless Build-UpLayer packaging) in October 2001. The core of the chip is the interconnection of the chip and the carrier. It is a bump, but the chip is buried directly inside the carrier. See Figure 25 to 27. (Although the BBUL process is still not mass-produced due to technical problems, the embedded component technology inside the PCB is the unremitting pursuit of the industry. And development direction).

(2) EPS/EAD: EPS (Embedded Passive Substrate), mass production in 2011; EAD (Embedded Active Device, embedded active components), mass production is rare. The internal buried passive components are shown in Figure 28 (this capacitor is slightly different from conventional capacitors).

(3) ECP®: AT&S has developed ECP® (Embedded Component Packaging) technology to embed active and passive components.

(4) SESUB: TDK developed SESUB (Semiconductor Embedded in SUBstrate) technology

(5) MCeP®: Shinko Electric has developed MCeP® (Molded Core embeddedPackage) technology to embed active and passive components.

(6) Coreless: including common Coreless and ETS (Embedded Trace Substrate), ETS is mostly used in low-end Flip Chip package (can improve yield and reduce cost), and rises in 2013.

(7) Padless: Padless is mainly used to improve wiring density and design flexibility.

(8) BSP (Blue Stencil Printing): In order to improve the production yield and efficiency of Fine pitch bump (SOP), Samsung Motor developed BSP in 2010 to replace the traditional Metal Mask.

(9) Via Post: ACCESS developed a copper column (via) technology for plating from the bottom of the hole, without laser drilling + plating filling

(10) MIS: Molded Interconnect Substrate (Molded Interconnect System, or Molded Interconnect System), originally developed by APSi (Advanpack Solutions Innovations), which uses epoxy resin as a substrate to form copper. Column technology. Currently, Substrate and the company are developing MIS technology. QDOS MIS, see Figure 37. Hengjin (PPt) named its MIS-like product C2iM® (Copper Connection in Molding).

In summary, various processes are used to produce a comparison of the manufacturing process capabilities and costs of the PCB shown in FIG.

In addition, various embedded component technologies for PSMA finishing

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